New Memory Technologies

DRAM technology faces fundamental scaling problems as we approach physical limits:

• Capacity: Capacitor size shrinks with process technology, making it harder to store enough charge for reliable sensing. Need more capacity for data-intensive workloads.
• Bandwidth: Off-chip pin count limited; bus speeds approaching signal integrity limits. Memory bandwidth is not scaling as fast as compute.
• Quality of Service (QoS): In multi-core systems, shared memory causes interference between applications. Hard to guarantee predictable latency.
• Energy: DRAM refresh consumes significant energy even when idle. Leakage power grows with capacity. Refresh overhead grows as more rows need refreshing in the 64ms window.
• Reliability: Smaller cells → more vulnerable to disturbance (Rowhammer), particle strikes, etc.

These challenges motivate research into new memory technologies that can complement or replace DRAM.

Phase Change Memory (PCM) uses chalcogenide glass that can exist in two phases:

• Crystalline: Low resistance → represents one bit value. Achieved by slow cooling (SET operation).
• Amorphous: High resistance → represents other bit value. Achieved by rapid heating + quenching (RESET operation).

Advantages of PCM:

• Better scaling: Scales to smaller process nodes than DRAM
• Higher density: Can store multi-bit per cell (MLC) — resistance levels, not just binary capacitor charge
• Non-volatile: Retains data without power for 10+ years. No refresh needed!
• Low idle power: No refresh energy when not being accessed

Disadvantages of PCM:

• Slow writes: Write latency ~10x longer than DRAM (heating/cooling the material takes time)
• Limited write endurance: Each cell can only be written ~10⁸ - 10⁹ times before wearing out (vs. effectively unlimited for DRAM). This is called write wearout.
• High write energy: Heating the material to change phase requires significant current
• Read is asymmetric with write: Reads are much faster than writes

Since neither DRAM nor PCM is perfect alone, hybrid memory systems combine them to get the best of both:

Property	DRAM	PCM
Speed	Fast (reads & writes)	Fast reads, slow writes
Endurance	Unlimited	Limited (~10^8)
Capacity	Limited by scaling	Large (denser)
Volatility	Volatile (needs refresh)	Non-volatile
Idle power	High (refresh leakage)	Low
Cost/bit	Higher	Lower

Design approaches:

• DRAM as a cache for PCM: Hardware-managed. DRAM acts like another level of cache in front of PCM main memory. Simple for software but limited by DRAM cache management overhead.
• DRAM and PCM as flat main memory: OS-managed. Both are part of the physical address space. OS places pages in DRAM or PCM based on access patterns. More flexible.

Key challenges:

• Data allocation: Which data goes in DRAM vs PCM? (Write-intensive → DRAM, read-mostly → PCM)
• Data movement: When/how to migrate pages between DRAM and PCM
• Wear leveling: Distribute writes evenly across PCM cells to avoid premature wearout of hot cells
• Requires changes across the stack: cache hierarchy, memory controller, OS page management