Notes/Instruction Set Architecture
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Instruction Set Architecture

L3L4L5Pre-Midterm

ISA design, addressing modes, CISC vs RISC

Topics Covered

Elements of an ISAAddressing modesInstruction processing styles (0/1/2/3 address)CISC vs RISCFixed vs variable length instructionsUniform vs non-uniform decodeLoad/store vs register/memory
01

Elements of an ISA

An ISA (Instruction Set Architecture) is the contract between software and hardware. It specifies:

  • Instruction sequencing model:
    • Control flow: Sequential execution with explicit branches (Von Neumann — most common)
    • Data flow: Execution determined by data availability (dataflow model)
  • Processing style (operand model):
    • 0-address (stack): Operands implicit on top of stack. E.g., PUSH A; PUSH B; ADD → pops top 2, pushes result. Compact code but limited parallelism.
    • 1-address (accumulator): One implicit operand is the accumulator register. E.g., LOAD A; ADD B → ACC = ACC + B. Simple but accumulator is a bottleneck.
    • 2-address: Source is also the destination. E.g., ADD R1, R2 → R1 = R1 + R2. Destroys one source operand.
    • 3-address: Separate source and destination. E.g., ADD R1, R2, R3 → R1 = R2 + R3. Most flexible, longest instructions.
  • Data types, registers, memory addressing, condition codes, etc.

Key Points

  • •0-address (stack): implicit operands on stack — compact but serial
  • •1-address (accumulator): ACC is implicit — simple but bottleneck
  • •2-address: source = destination — destroys one operand
  • •3-address: separate src/dest — most flexible, longest encoding
02

Addressing Modes

Addressing modes specify how to compute the effective address of an operand:

  • Absolute (Direct): Address is in the instruction. LOAD R1, [0x1000]
  • Register Indirect: Address is in a register. LOAD R1, [R2]
  • Displaced (Based): Register + constant offset. LOAD R1, [R2 + 100]. Common for struct field access, stack frames.
  • Indexed: Base register + index register (possibly scaled). LOAD R1, [R2 + R3*4]. Common for array access.
  • Memory Indirect: Address in memory points to the actual address. LOAD R1, [[R2]]. Pointer dereference. Requires two memory accesses.
  • Auto-increment/decrement: Register is updated after/before access. LOAD R1, [R2++]. Useful for sequential array traversal.

Trade-off: More addressing modes → more flexible for programmer/compiler, but harder to decode and potentially slower.

Key Points

  • •Absolute: address in instruction. Register indirect: address in register
  • •Displaced: reg + offset (struct fields, stack). Indexed: reg + reg*scale (arrays)
  • •Memory indirect: pointer-to-pointer (2 memory accesses)
  • •Auto inc/dec: update register after access (array traversal)
  • •More modes = more flexibility but harder to decode
03

CISC vs RISC & Instruction Encoding

CISC (Complex Instruction Set Computer): e.g., x86

  • Many complex instructions (string ops, BCD arithmetic, etc.)
  • Variable-length instructions (1-15 bytes in x86)
  • Instructions can access memory directly (register-memory architecture)
  • Non-uniform decode (different formats per instruction class)
  • Fewer instructions per program, but each takes more cycles

RISC (Reduced Instruction Set Computer): e.g., MIPS, ARM, RISC-V

  • Simple, regular instructions
  • Fixed-length instructions (32 bits typically)
  • Load/store architecture: Only load/store instructions access memory; ALU operates on registers only
  • Uniform decode (few formats, regular field positions)
  • More instructions per program, but each completes in fewer cycles

Instruction length trade-offs:

  • Fixed length: Easier decode, simpler fetch (always know where next instruction starts), but wastes bits (padding for short instructions)
  • Variable length: More compact code (good for I-cache), but complex decode (must parse instruction to find length and next instruction)

Uniform vs non-uniform decode:

  • Uniform: Same bits always mean the same thing (opcode always in same position) → fast, simple decode
  • Non-uniform: Field meanings depend on opcode → requires more complex decode logic

Load/store vs register/memory:

  • Load/store: Only explicit load/store instructions touch memory. ALU instructions only use registers. Simple pipeline, easy to determine when memory is needed.
  • Register/memory: ALU instructions can have memory operands. More compact code but complicates pipeline (memory access stage needed for ALU instructions).

Key Points

  • •CISC: complex instructions, variable-length, register-memory, non-uniform decode
  • •RISC: simple instructions, fixed-length, load/store, uniform decode
  • •Fixed length = easy decode but wasted bits; variable = compact but hard decode
  • •Load/store: only loads/stores touch memory (simpler pipeline)
  • •Register/memory: ALU can use memory operands (compact but complex pipeline)
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Exam Tip

Know the 4 key RISC properties: fixed-length, load/store, uniform decode, simple instructions. Understand WHY each property simplifies the microarchitecture.

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